Courses Offered

VLSI Verification Course

Course Objectives

VLSI Verification course is a comprehensive training program on ASIC Design and Verification, with the course syllabus extending from basics of Digital Electronics and Verification concepts, all the way up to building complex Verification environments using UVM.
An all-inclusive one-stop solution to transform you into a Professional VLSI Design and Verification Engineer of current day industry standards.

Eligibility

BE/BTech – ECE, EEE, CSE, E&I.
Equivalent Master Engineering Degrees., M.Sc. Electronics

Best VLSI Verification Training in Bangalore & Chennai
Course Content

DIGITAL ELECTRONICS

Week 1
  • Combinational Logic
  • Introduction to Logic Gates
  • Combinational Logic Circuits
  • Sequential Logic Circuits
  • Frequency Division Using Counters
Week 2
  • Finite State Machine
  • Synchronous and Asynchronous Digital Circuits
  • Clock Domain Crossing
  • Low Power Design Techniques
  • Setup and Hold time

VERILOG HDL

Week 3
  • Introduction to Verilog
  • Data Types
  • Operators
  • Compiler Directives and System Tasks
  • Task & Function
  • Data Flow Modeling
  • Behavioral Modeling
Week 4
  • Verilog for Design
  • Combinational Logic Design
  • Sequential Logic Design
  • Synthesizable Syntaxes for Design
Week 5
  • Verilog for Verification
  • Timing Controls
  • Conditional Statements
  • Loops
  • Sequential and Parallel Blocks
Week 6
  • Finite State Machine
  • Advanced Verilog for Verification
  • Timing Checks
  • Lab

SYSTEM VERILOG ( SV )

Week 7
  • Data Types
  • Arrays
  • Queue
  • Array Manipulation Methods
Week 8
  • Structures
  • Unions
  • Task and Function
  • Task and Function Argument Passing
Week 9
  • Interface
  • Virtual Interface
  • SV Classes
  • Mailbox
Week 10
  • Packages
  • Compilation Unit
  • Processes
  • Randomization and Constraints

UNIVERSAL VERIFICATION METHODOLOGY

Week 11
  • UVM Introduction
  • UVM Factory and Overrides
  • UVM Reporting
  • UVM Transaction Level Modeling
  • Lab
Week 12
  • UVM Driver
  • UVM Sequencer
  • UVM Monitor
  • UVM Agent
  • UVM Environment
  • UVM Test
  • Lab
Week 13
  • UVM Phases
  • UVM Sequence
  • Virtual Sequence and Virtual Sequencer
  • UVM Scoreboard
  • UVM Callbacks
  • Lab
Week 14
  • UVM Configuration
  • Register Abstraction Layer(RAL)
  • Functional Coverage Model and Subscriber
  • Reference Model
  • Lab

EDA Tools

Cadence Simulator
Xilinx Vivado

Projects [ Industry Oriented Projects]

Build Verification IP for any one of the industry standard protocols like DDR,AXI Matrix and PCIe( TL ).

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