Professional Development course on VLSI Verification (5 months Full time course)
Ampere VLSI Academy, a division of Mobiveil Technologies, offers a high-profile VLSI Verification course in the field of Semiconductor design. Ampere VLSI Academy, a division of Mobiveil Technologies, has structured the course to have right mix of lectures combined with lab projects to transform a graduate engineer to a skilled work force in Verification domain which is on demand today across the globe.
At Ampere VLSI Academy, a division of Mobiveil Technologies, our mission is to empower electronics graduates to realize their full potential by imparting specialized knowledge and practices required by the semiconductor Industry.
A graduate / Post Graduate with Electrical/ Electronics / Communication/ Computer engineering background will benefit from this training platform which is designed to meet the current industry needs.
Ampere VLSI Academy , a division of Mobiveil Technologies, course differentiates from similar courses in the following ways
Salient features of the Course
Course Duration
Course Eligibility/In-take Procedure
Placement Assistance
Course Contents
Course Duration – 5 Months
Semiconductor Overview
- ASIC/FPGA Technologies & Flow
- EDA Tools
Digital Electronics - Duration. 10 days
- Introduction To Logic Gates
- Combinational/Sequential Logic Circuits
- Frequency Division Using Counters
- Finite State Machine
- Synchronous and Asynchronous Digital Circuits
- Clock Domain Crossing, Low Power Design Techniques
- Setup And Hold Time
Verilog HDL - Duration. 15 days
- Introduction to Verilog, Data Types, Operators
- Compiler Directives And System Tasks
- Task & Function, Data Flow Modeling
- Behavioral Modeling, Verilog For Design
- Combinational/Sequential Logic Design
- Synthesizable RTL For Design
- Verilog For Verification, Timing Controls
- Conditional Statements, Loops
- Sequential And Parallel Blocks
- Advanced Verilog For Verification, Timing Checks
Verification Concepts - Duration. 5 days
- Real-time verification scenarios
System Verilog - Duration. 20 days
- Data Types – Arrays, Queue
- Array Manipulation Methods
- Structures, Unions, Task And Function
- Task and Functions
- Interface, Virtual Interface, SV Classes
- Mailbox, Packages, Compilation Unit, Processes
- Randomization And Constraints, SV Assertions
Protocol Training - Duration. 10 days
- PCIe or DDR or AXI
UVM - Duration. 20 days
- UVM Introduction, Factory and Overrides
- UVM Reporting, Transaction Level Modeling
- UVM Driver, Sequencer, Monitor, Agent
- UVM Environment, Test, Phases, Sequence
- Virtual Sequence and Virtual Sequencer
- UVM Scoreboard, Callbacks, Configuration Management
- Register Abstraction Layer(RAL)
- Functional Coverage Model and Subscriber
- Reference Model
Real Time Project Training - Duration.20 Days
- Students will get a chance to work on a Active Real Time Project involving AXI Interconnect/PCI Express and build their professional expertise.